The present invention relates to integrated circuit structures and fabrication processes and more particularly to a silicon on insulator (SOI) class of products. In particular, these structures and processes involve epitaxial silicon regions electrically isolated by silicon dioxide dielectric from a silicon substrate.
SOI, as a general class of technology, has been in existence for a number of years, but has remained of somewhat limited applicability by virtue of its prevailing use of expensive sapphire as the substrate material. The benefits of SOI devices, including, among others, the absence of CMOS latch up problems and the elimination of fabrication steps need to isolate active regions, are well known. Heretofore, attempts to create monocrystalline silicon regions which are isolated by silicon dioxide dielectric from the silicon substrate have proven to be difficult and, consequently, not found significant commercial following. A representative approach is described in U.S. Pat. No. 4,604,162. Numerous similarly directed approaches appear in processes pursuing three dimensional integration. Although such processes and concluding structures are effective for limited application, their complexity and yield limitations have left them more as laboratory curiosities.
Some very recent works with similar objectives have revived heretofore discarded integrated circuit fabrication concepts involving, first, the formation of underlying porous silicon regions and, second, the oxidization of such formal regions to create isolating dielectrics beneath regions of epitaxial silicon. For instance, exemplary techniques are described in the article entitled "Porous Silicon Techniques for SOI Structures" by Tsao, which appeared in the Nov. 1987 issue of IEEE Circuits and Devices, page 3-7. The article provides an overview of how porous silicon can be used to create SOI structures. The anodization by which porous silicon regions are formed beneath defined active regions is selectively constrained by impurity type junction patterns. Thermal oxidation is used to convert the porous silicon into silicon dioxide.
The article entitled "SOI Technology Using Buried Layers of Oxidized Porous Si" by authors Barla et al., which appeared on pages 11-14 of the aforementioned technical publication, describes a fabrication technique in which successive epitaxial layers of different impurity concentration are blanket deposited in succession upon a silicon substrate, and then photolithographically masked and etched to selectively access areas of the underlying and highly doped layer susceptible to anodization. The porous silicon layer created by the anodization is thereafter oxidized to electrically isolate any overlaying epitaxial layers. A somewhat more refined variation on this fundamental technique is disclosed in U.S. Pat. No. 4,628,591, wherein the number of epitaxial layers has been increased and selectively varied in respective impurity concentration.
U.S. Pat. No. 4,716,128 sets forth a technique for forming active devices on epitaxial silicon. However, the active devices in the concluding structure are not isolated by dielectric from the substrate, the process does not involve the formation of a porous silicon underlayer, and the end product is a field effect transistor structure per se, unique in providing source/drain regions above the sidewalls of the epitaxial region. Accordingly, the reference merely confirms that epitaxial silicon may be selectively grown and thereafter used to form active devices.
There presently remains a need for a SOI fabrication process which utilizes oxidized porous silicon in a highly reproducible manner to create dielectrically isolated epitaxial silicon islands with accentuated decoupling from the substrate body.